A prior art display device for both a character display and a graphic display is illustrated in FIG. 1. The display panel of the cathode ray tube (CRT) used in the display device of FIG. 1 is illustrated in FIG. 2, and the memory field of the display device of FIG. 1 is illustrated in FIGS. 3 and 4.
In FIG. 3, the vertical length of the memory field is divided into 16 character rows and the horizontal length of the memory field is divided into 32 character columns, and hence the entire memory field is divided into 512 (=32.times.16) sectional areas. Each of the sectional areas provides space for one character.
Each of the sectional areas consists of 96 picture elements (bits) which are arranged in 12 lines in the vertical direction and 8 bits in the horizontal direction. As an example, the composition of the sectional area "Row 1-Column 17" of the memory field of FIG. 3 is illustrated in FIG. 4.
Thus, the entire memory field consists of 49152 (=512.times.96) picture elements, and simultaneously of 512 sectional areas.
The bit signal "1" causes the corresponding bit of the display panel of the CRT 1 as display means to be luminous while bit signal "0" causes the corresponding bit of the display panel of the CRT 1 as display means to remain non-luminous.
The display device of FIG. 1 comprises a central processor unit 1, a clock signal generator 2, a data bus 10, an address bus 11, a data RAM, a program ROM, a display signal generating circuit 5 and a CRT 6 as display means. The display signal generating circuit 5 comprises a circuit 51 for generating timing pulses for display, an address decoder circuit 52, an address switching circuit 53, a display RAM 54, a discrimination signal RAM 55, a character pattern ROM 56, a switching circuit 57, and a circuit 58 for converting parallel signals into series signals.
The central processor unit 1 conducts an operation of, for example, 1 through 8 bits parallel calculation. The address bus 11 consists of 16 parallel conductors. The data bus 10 consists of 8 parallel conductors, through which said 1 through 8 bits parallel calculation signal are communicated between the central processor unit 1 and each of the data RAM 3, the program ROM 4, the display RAM 54, and the discrimination signal RAM 55. In order to separate communications between the central processor unit 1 and the memories 3, 4, 54 and 55, different addresses are allotted to the memories 3, 4, 54 and 55. An example of the allotment of the addresses is illustrated in the portion (A) of FIG. 5. The addresses are expressed in hexadecimal numbers. In the present specification hexadecimal numbers are described with the indication "16".
The program ROM 4 stores the program for operating the display device of FIG. 1. The display RAM 54 stores the picture information in the positions of the display RAM 54 which correspond to the positions of the display panel (FIG. 2 and FIG. 3). The discrimination signal RAM 55 stores the information which discriminates whether the information in question of the display RAM is a graphic data or a character data. The character pattern ROM 56 stores picture pattern data for character data and converts only the character data from the display RAM 54 into picture pattern data.
The sequence of the addresses in the device of FIG. 1 is illustrated in FIG. 5. The addresses are expressed in hexadecimal numbers 000016 through FFFF16. The addresses from 000016 through OFFF16 are allotted for the data RAM 3. The addresses from 800016 through 97FF16 are allotted for the display RAM 54. The addresses from A00016 through B7FF16 are allotted for the discrimination RAM 55. The addresses from F00016 through FFFF16 are allotted for the program RAM. Such allotment is illustrated in portion (A) of FIG. 5.
The constitution of the address region A00016 through B7FF16 for the discrimination RAM is illustrated in the portion (B) of FIG. 5. The constitution of the address region 800016 through 97FF16 for the display RAM is illustrated in the portion (C) of FIG. 5. The constitution of the address regions for Row 1 is illustrated in the portions (D1) and (E1) of FIG. 5. The constitution of the address regions for Row 2 is illustrated in the portions (D2) and (E2) of FIG. 5.
The discrimination signals stored in the addresses from "00016" through "B7FF16" of the discrimination RAM 55 corresponds to the signals stored in the addresses from "800016" through "97FF16" of the display RAM 54. The value of the discrimination signal is "0" when the discrimination signal represents the character information, and is "1" when the discrimination signal represents the graphic information.
The information stored in the addresses from "800016" through "97FF16" of the display RAM 54 are read out simultaneously with the reading out of the information stored in the addresses from "A00016" through "B7FF16" of the discrimination RAM 55.
The upper four bits of the binary expressions of the above mentioned addresses are "10002" and "10102", where 2 indicates the binary expression. It is observed that only the third bit "0" from the top of "10002" is different from the third bit "1" from the top of "10102". Therefore, the display address signal of only the lower 13 bits, which is equal to 16 bits minus upper 3 bits, is supplied from the timing pulse generator 51 through the address switching circuit 53 to the load of the address switching circuit 53.
As illustrated in FIG. 5, in the device of FIG. 1, the character information in the form of the character code must be stored in every line of one section, e.g. in twelve lines of one section of the memory field of FIG. 3. However, although the repetitive storage of the character information is not indispensable, a longer time is required to conduct the writing-in of the information to memory devices. Such an extension of time for the operation of the central processor unit 1 prevents the display device from speeding-up its operation.
Also, it is disadvantageous that the display device of FIG. 1 requires a display RAM 54 and a discrimination signal RAM 55 both of a relatively large capacity which make the display device of FIG. 1 considerably expensive.
An example of prior art CRT display device for both the character display and the graphic display is disclosed in "CRT Controller (CRTC) HD46505R Users Manual", published by Hitachi Limited in 1979.